(1) Field of the Invention
The present invention relates to a dual port type semiconductor memory device such as a first-in first-out (FIFO) memory in which a write operation and a read operation are carried out in parallel.
(2) Description of the Prior Art
In a prior art FIFO memory, a write operation and a read operation are carried out in parallel at a memory cell array. The write operation is carried out by a write pointer. That is, the write pointer is reset by a write reset signal and counts a write clock signal after receiving this write reset signal. As a result, the write pointer writes input data into the i-th address location of the memory cell array, where i is
the count value of the write clock signal (i=0, 1, 2, . . . ). On the other hand, the read operation is carried out by a read pointer. That is, the read pointer is reset by a read reset signal and counts a read clock signal after receiving this read reset signal. As a result, the read pointer reads data from the j-th address location of the memory cell array, where j is the count value of the read clock signal (j=0, 1, 2, . . . ).
In this prior art memory, however, the reading time is long, which will be later explained in more detail.